Structure of processor

Introduction

; The architecture of a Processeur is the fitting of its components; this fitting is made for a task or of a whole of precise tasks envisaged by the originator.

To know that a processor has a Instruction Add which makes an addition between two registers and puts the result in a third relates to the architecture of the processor.

; The implementation or microphone-architecture' is the logical organization of the data flows and control of those.

To know that a processor has two arithmetic units able to carry out this instruction relates to microphone-architecture.

; The manufacture is the material concretization of the implementation.

To know that these arithmetic units are carried out in a technology CMOS with three metal levels and an intricacy of engraving of 130 nanometers relates to the realization.

For a given architecture, one can have several Implementation S and a given implementation can be used as a basis with several achievements. For example architecture System 360 of IBM was available from the beginning into five different implementations having naturally performances and a different cost (it is besides in context of the definition of this architecture that nomenclature above was refined) and nowadays them microprocessors of Intel and AMD provide the many ones examples of the two kinds of variation.

Naturally the interactions between the three levels are complexes. The constraints of realization limit them microarchitectural choices and the desire to be able to choose a given implementation influence the definition of architecture. If advantages of compatibility force to want to keep constant architecture, to want to have an implementation and an effective realization push towards an evolution, that is to say by compatible extension (addition of instructions for example), that is to say while specifying fuzzy zones or even while invalidating what formerly was authorized.

Structure of a processor

A processor comprises three classes of components:

of storage spaces, source of the instructions and their operands and destination of the results;

of the functional units, carrying out handling on the operands and providing the results;

a controller, reading the instructions and coordinating their execution by the other components.

Storage spaces

Information is primarily recorded in the registers, a register being a space of memory which has a significant name and a definite format making it possible the processor to quickly store temporary information. The number of the registers depends on the type of processor and the manufacturer. Several specific instruction sets for applications of multi-media style have also their own registers for a treatment more specific and fast of information.

In addition to this memory, the processors (according to their type) have a memory with very low latency of access. This memory, called mask , arises on various levels (the top-of-the-range processors have about it up to three level) which are noted L1 L2 and L3. The larger this memory is, the more the processor can store information and thus reduce the access to the components having a higher latency.

Workspace

It is the whole of the sites easily spécifiables who contain the operands and them temporarily results of the operations. These sites are often called registers .

It is absolutely not necessary that the registers are homogeneous although one can often group the registers in classes, so that the registers of a class can to be used in the place of any other register of the same class. But it is not rare that a class does not comprise that only one register.

Architectures have almost all at least two classes registers: to store the whole values, one to store the numbers represented in floating decimal point. But often, the workspace comprises registers having particular functions.

; An accumulator: is a register being used as implicit source with the majority of the instructions and containing the result after their execution.

; Index registers: are registers being used with calculation as address (see further).

; A pointer of pile: indicating the address of the top of a pile managed by the processor.

; A frame to point : being used to reach the local data of the routine in the course of execution.

Certain registers have a particular behavior: they inform state of the processor or contain information by the way last operations carried out (for example an indicator indicating if the last result were null or not). Among these particular registers one often finds:

; The instruction counter ( program counter , instruction to point ): indicating the instruction address in the course of execution or of next instruction to be carried out;

; the status word: gathering the most important information on the state of the processor.

Memory capacity

Contrary to the workspace, a memory capacity seems a unit homogeneous of sites, each one of those being specified by its address.

The majority of the processors have only one memory capacity, but some have some several (by example a microcontrolor can have a memory capacity on the circuit and a memory capacity outside this one).

Sometimes a memory capacity can be plunged in another, i.e. the same site can be accessible at an address from a given memory capacity or at another address from another memory capacity. It is sometimes the case for whole or part of the registers of the workspace.

The modes of addressing of the processor are the various ways in which one can specify operands of an instruction. Among the possible modes of addressing, let us quote:

; implied addressing: the operand is not specified in the instruction; it is always the same one (for an instruction of incrementing for example, one can consider that one operand is always constant 1), that is to say it is in a fixed register (so much instructions implicitly use the same register, this one is named the accumulating ), that is to say its address is in a fixed register (for example the pointer of pile).

; immediate addressing: the value of the operand is given directly in the instruction;

; direct or specific coding: the address of the operand is given directly in the instruction;

; addressing by register: the operand is in a register given in the instruction;

; indirect addressing by register: the address of the operand is in a register;

; indirect addressing: the address of the operand is in a site report whose address is given in the instruction;

; indexed addressing: the address of the operand is formed by adding the contents with one or two registers and a constant.

Left entry

For the programmer, the management of the left entries is done often exactly like if one reached a particular storage space. According to architectures it appears is as registers (it is often the case in the microcontrôleurs), that is to say as a memory capacity (in which case the modes of addressing are often more reduced that in the normal memory capacities). Sometimes, the left entries are done while reaching simply at particular addresses in the normal memory capacity.

Classification of architectures

Structure CISC

See Complex instruction set computer.

RISC architecture

See Reduced instruction set computer.

Structure VLIW

See

Processor VLIW
VLIW.

Vectorial architecture

See too

Internal bonds

External bonds

a simulator of processor MIPS simplified

Books

Computer Structures , G.A. Blaauw and F.P. Brooks Jr,

Addison Wesley

Computer Structures, has Quantitative Approach ,

J.L. Hennessy and D.A. Patterson, Morgan Kaufmann

Microprocessors, has programmer' S view , R.B.K. Dewar

and Mr. Smosna, Mc Graw Hill

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